Generally, in a common prior art fabrication method, bipolar transistors are fabricated in a relatively simple diffusion method that can be adapted to other manufacturing processes, such as the well known CMOS process. In a typical example, a substrate doped for p-type conduction is provided. A well of n-type conduction is formed in the substrate by ion implantation and drive-in or diffusing an impurity into the substrate. An insulating layer is formed on the surface of the substrate, generally during, or as a step in, the CMOS manufacturing process, and three spaced apart openings are formed in overlying relationship to the n-type well to define an emitter, base and collector. A smaller well of p-type conduction is then formed in the n-type well so as to be spaced from the sides and bottom of the n-type well and so that the emitter and base openings overlie the p-type well and the collector opening overlies the n-type well. An emitter is then diffused or implanted in the emitter opening and base and collector contacts are diffused or implanted in the base and collector openings, respectively.
The major problem with this prior art bipolar transistor is the fact that the depth of the p-type well between the emitter and the n-type well is the thickness of the base and this thickness determines the speed or frequency response of the bipolar transistor. Because of the spreading of the diffusion, or implant and anneal, it is difficult to control the base thickness and impossible to make it thin enough to arrive at a very high frequency device. Generally, these prior art bipolar transistors are limited in frequency response to below 500 MHz, and usually operate at 300 MHz or below. However, these prior art bipolar transistors did have a relatively good collector-to-emitter breakdown voltage (BV.sub.CEO).
The problem of a low frequency response was solved in another prior art bipolar transistor utilizing sub-collector epitaxially grown layers (epi layers) on the surface of the substrate along with narrow base width. In this prior art bipolar transistor, a heavily doped sub-collector is formed in the surface of the substrate and an epi layer is grown over the top so that the heavily doped layer becomes a buried conductive layer. An insulating layer is formed on the surface of the epi layer and three spaced apart openings are formed in the insulating layer to define an emitter, base and collector. A very thin intrinsic base is formed in the emitter opening. An extrinsic base is formed in the base opening and connected to the intrinsic base through the epi layer in some fashion, generally with a diffusion or implant. An emitter is formed in overlying relationship to the intrinsic base. Also, a deep diffusion or implant is formed in the collector opening which is deep enough to be in contact with the buried layer and a collector contact is formed in the collector opening in contact with the deep diffusion.
This epi layer bipolar transistor can be fabricated with a very high frequency response, in a range of 300 MHz to 10 GHz. The epi layer is generally grown very thin so that the spacing between the intrinsic and extrinsic bases and the buried layer is relatively small. However, the BV.sub.CEO of the transistor is reduced. Generally, the BV.sub.CEO of high performance epi layer bipolar transistors is below 9 volts and for very high frequency bipolar transistors may be below 5 volts.
Another major problem with epi layer bipolar transistors is the fact that the fabrication process is very long, complicated and expensive. Also, the epi layer bipolar fabrication process is incompatible with standard CMOS process. Therefore, the epi layer bipolar transistors add substantially to the cost of manufacturing, if there is an attempt to integrate them into other fabrication processes (if integration is even possible).
Thus, it would be desirable to provide an improved bipolar transistor which incorporates a high frequency response with a relatively high BV.sub.CEO and fabrication techniques compatible with standard CMOS, HVCMOS and SMART POWER fabrication processes.
It is a purpose of the present invention to provide a new and improved high performance, high voltage non-epi bipolar transistor.
It is another purpose of the present invention to provide a new and improved high performance, high voltage non-epi bipolar transistor which is fabricated by methods which are CMOS and HVCMOS compatible.
It is yet another purpose of the present invention to provide a new and improved high performance, high voltage non-epi bipolar transistor which is incorporated into CMOS and/or HVCMOS fabrication.
It is still another purpose of the present invention to provide a new and improved method of fabricating a high performance, high voltage non-epi bipolar transistor at a relatively low cost.
It is a further purpose of the present invention to provide a new and improved high performance, high voltage non-epi bipolar transistor having a relatively high speed and high cutoff frequency.
It is yet a further purpose of the present invention to provide a new and improved high performance, high voltage non-epi bipolar transistor with a high BV.sub.CEO relative to the speed/ cutoff frequency of the bipolar transistor.
It is still another purpose of the present invention to provide a new and improved high performance, high voltage non-epi bipolar transistor with an inherently high yield.